1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly to a method for reducing poly-depletion in a dual gate CMOS fabrication process.
2. Description of the Prior Art
As generally known in the art, MOSFET gates are formed of polysilicon with properties required for a gate, such as high melting point, easy formation of a thin film, easy line patterning, stability in oxidizing atmosphere and planarization. Actually, polysilicon gates in a MOSFET contain dopants, such as phosphorus (P), arsenic (As) and boron (B), thereby realizing a low resistance.
Conventional CMOS devices form N+ polysilicon gates in both NMOS and PMOS regions. However, a buried channel is formed by the count doping in the PMOS region to adjust a proper threshold voltage, which may increase short channel effects resulting in the degradation of device performance.
In an attempt to overcome such drawbacks, a dual gate CMOS which forms an N+ polysilicon gate in the NMOS region and a P+ polysilicon gate in the PMOS region has recently been introduced.
The fabrication of a dual gate CMOS is a process employing N+ polysilicon for the NMOS gate and P+ polysilicon for the PMOS gate. The process generally comprises the steps of depositing an undoped amorphous silicon (a-Si) or an undoped polysilicon (poly-Si) as a gate material, selectively implanting an N+ ion and a P+ ion into the NMOS and PMOS gates, respectively, and performing a thermal diffusion to uniformly distribute dopants over the entire gate regions.
However, poly-depletion may occur during the conventional process of fabricating a dual gate CMOS due to ion-implantation with an insufficient dose or energy and incomplete thermal diffusion.
The poly-depletion may be caused due to insufficient doping within a polysilicon film. Part of a voltage applied to the gate for channel inversion is applied to the depletion region at the polysilicon bottom, which consequently increases a threshold voltage Vt and the thickness of a gate dielectric film while reducing an on current.
The level of depletion at the polysilicon bottom is highly dependent on the thickness of polysilicon. Accordingly, the threshold voltage Vt has a great variation over the entire wafer, which makes it difficult to manage the proper target of the threshold voltage Vt and causes the reduction of yield.
Doping efficiency, as an index showing the poly-depletion level, is indicated by a percentage of the inversion gate capacitance relative to the accumulation gate capacitance. Generally, appropriate doping efficiency is about 95%. Such appropriate doping efficiency can be maintained when suitable ion implantation conditions and thermal budget are secured.
The poly-depletion may further increase due to narrowing of the gate linewidth. In submicron devices having a gate length or width of less than 0.2 μm, poly-depletion caused by a short length and/or by a narrow width of gates is added to one-dimensional poly-depletion caused by a vertical electric field in gates, thereby generating a three-dimensional poly-depletion effect. The 3D poly-depletion effect caused by the reduction of the gate length or width is based on the following two mechanisms.
The first mechanism is that additional depletions occur at the gate sidewalls due to the fringing gate fields. The additional depletions at the gate sidewalls can be ignored when the gate is long. However, as the gate length is scaled down, the additional depletions increase and the average level of depletions in the entire channel also increases. Accordingly, doping efficiency is reduced as the gate length is shorter. (C. H. Choi, et al., IEEE Electron Device Letters, Vol. 23, No. 4, p. 224, 2002)
FIGS. 1a and 1b are views for explaining the poly-depletion effect depending on the gate linewidth, wherein drawing reference numeral “11” is provided for a silicon substrate, numeral “12” for a gate dielectric film, numerals “13a” and “13b” for polysilicon gates having different linewidths, numeral “14” for a depletion region and numeral “15” for a sidewall region with additional depletion which is caused by a fringing field.
As shown in the above drawings, sidewall depletions caused by the fringing gate fields are increased as the gate is linewidth is reduced. Also, a narrow gate linewidth reduces the doping efficiency.
The second mechanism of the poly-depletion effect is that the reduction of channel width further increases the poly-depletion effect due to so-called TRISI-NWE (Trench Isolation Step-Induced-Narrow Width Effect) produced by STI (Shallow Trench Isolation). (Youngmin Kim, et al., IEEE Electron Device Letters, Vol. 23, No. 10, p. 600, 2002)
FIGS. 2a and 2b are views for explaining the poly-depletion effect depending on the channel width, wherein drawing reference numeral “21” is provided for a silicon substrate, numeral “22” for an STI oxide film, numerals “23a” and “23b” for channels and numeral “24” for a polysilicon film.
As shown in FIGS. 2a and 2b, the difference between the height of the STI oxide film 22 and that of the silicon substrate 21, i.e., EFH (Effective Fox Height; height of field oxide measured at the top of the silicon substrate), is generally a positive number. Accordingly, the polysilicon film 24 becomes relatively thicker in border portions (indicated by oblique lines in the drawings) where it adjoins both the STI oxide film 22 and the channel 23a or 23b, because of the conformal deposition property of polysilicon.
As the polysilicon film 24 is getting thicker, the poly-depletion effect is further increased at the bottom of the polysilicon film 24 (below the dotted lines in the drawings). As a result, the poly-depletion effect becomes more significant at the edges of the channel, which consequently reduces the channel width. The average level of poly-depletion over the channel is raised due to the increase of the sidewall depletion, resulting in the reduction of the doping efficiency.
The explained above are two representative mechanisms relating to the three dimensional poly-depletion effect. The increased poly-depletion effect increases the absolute value of the threshold voltage Vt and the variation of the threshold voltage Vt within the wafer. Therefore, as higher integration is pursued, it is required to reduce the poly-depletion effect for the management of a stable threshold voltage Vt.
Cell transistors used in FCMOS SRAM devices of less than 0.14 μm have channel length and width of less than 0.2 μm that may bring about serious three-dimensional poly-depletion. Management of a stable threshold voltage Vt for these transistors is of critical importance to a low voltage operation yield.